In today's electronic marketplace, increasing emphasis is being placed upon rapid response to market demands. This emphasis is driven, at least in part, by the accelerating rate of change of semiconductor technology, particularly digital integrated circuit technology. Any product which lags the current state of technology by too great a margin may easily find itself left behind, as other, more sophisticated products dominate the marketplace. As a result, there are extreme pressures on electronic system designers to produce highly-complex, reliable digital systems in what would once have been considered impossibly short time frames. In order to meet size, space, and power dissipation constraints, custom (or semi-custom) integrated circuits are often necessary.
In response to these, and other, perceived needs, digital designers have turned to semi-custom integrated circuit design techniques, such as gate arrays and standard cells, to shorten the integrated circuit design cycle. Integrated circuits of this type are commonly referred to as ASICs or Application Specific Integrated Circuits, and are generally based upon pre-defined physical and functional integrated circuit building blocks which a designer can "plug" together rapidly to provide a desired function.
Of particular interest are standard-cell ASICs, wherein the functional building blocks are provided to the designer as "standard cells", in other words, as standard, pre-designed and pre-characterized (and fully tested) function modules (or cells). In addition to elementary logic functions, (such as gates, flip-flops, multiplexers, decoders, etc.) these function modules often include much higher level functions such as ALU's, multipliers, peripheral controllers, and complete microprocessors. Relatively large, complex standard cells are often termed "megacells". For any given semiconductor technology, these functional modules (e.g., circuit blocks) tend to have a corresponding standard shape, size and layout for which their electrical properties and responses have been completely characterized.
For the purposes of this specification, a "standard-cell" is defined as a pre-defined circuit function, which has a standard layout for inclusion on an integrated circuit die. For the purposes of this discussion, it is assumed that a megacell is physically larger than a cell, although either can be a standard cell.
By using standard cells in an integrated circuit design, a designer can manipulate highly-complicated digital functions while remaining highly confident that these functions are thoroughly tested over a wide range of operating characteristics and that they will perform according to their specifications. For example, a designer can incorporate a microprocessor megacell into a larger integrated circuit design almost as easily as one could incorporate an off-the-shelf (packaged, stand-alone) microprocessor into a printed circuit board design. It is generally accepted that the use of standard cell techniques can be used to design and obtain highly complex digital systems in significantly less time than might otherwise be possible. A designer can also incorporate non-standard surrounding logic into a design in addition to a microprocessor megacell. For purposes of this discussion, such surrounding logic is deemed to be divisible into distinct cells.
Standard-cell technologies are not without their problems and trade-offs, however. Large, pre-defined megacells generally have large, inflexible pre-defined shapes which restrict integrated circuit layout options (i.e., the ability to incorporate and interconnect other cells on the same chip). Interconnections between cells on opposite sides of a megacell must generally be routed around the megacell, thereby creating long signal paths. Further, these long signal paths tend to occupy an inordinate amount of space on the integrated circuit, thereby increasing the overall size of the die (integrated circuit chip). Longer signal paths also result in longer signal delays which can limit circuit performance. Since the cost of integrated circuits is closely related to die size, poor die area utilization (due to the space required for signal routing) leads to increased cost.